OpenLM License Parser Engineering Software Catalog

OpenLM License Parser Engineering Software Catalog

List of License Managers - Vendors for FLEXlm - Features for cdslmd

...Finished Indago_DA_App
CMM (11) Indago_DA_wAPI
Medina-MEDPRE70 (93) Indago_ESW_DBG
11300 Innovus_10nm_Opt
11400 Innovus_20nm_Opt (2)
11701 Innovus_3D_IC_Opt
11702 Innovus_5nm_Opt
11703 Innovus_7nm_Opt (2)
11710 Innovus_C
12110 Innovus_CPU_Opt (2)
12111 Innovus_DFM
12121 Innovus_DFM_Opt
12141 Innovus_GigaPlace_XL_Opt
12141_64bit Innovus_hfr_Opt
12150 Innovus_Hier_Opt (1)
12500 Innovus_Impl_System (8)
14000 Innovus_Impl_System_Basic (33)
14010 Innovus_MCPU_Opt
14020 Innovus_MS_Opt
14030 Innovus_PI_Opt
14040 Integrated_Metrics_Center (10)
14060 Integrated_Metric_Center
14100 Integ_Design_Mfg_L
14101 Interposer_Extract
14110 intrgloss
14111 Intrica_powerplane_builder
14120 intrroute
14130 intrsignoise
14140 IPB_2S10PUC_ALL
14400 IPB_2S15PUC_ALL
14410 IPB_2S20PUC_ALL
14420 IPB_2S40PUC_ALL
Medina-DSMON IPB_2S60PUC_ALL
20120 IPB_2SUPUC_ALL
20121 IPB_4S10PUC_ALL
20122 IPB_4S20PUC_ALL
20123 IPB_4S40PUC_ALL
20124 IPB_4S60PUC_ALL
20127 IPB_4SUPUC_ALL
20128 IPB_6S60PUC_ALL
20220 IPB_6S90PUC_ALL
20221 IPB_6SUPUC_ALL
20222 ipc_in
20227 ipc_out
Medina-PAMCRASH (7) IPlaceBase
Medina-STARCD IPlaceBase_ALL
21000 IPO
21060 ISLAND (1)
21200 jaspercore
21400 (7) jaspergold
2141 jasper_advp
21900 jasper_afl (1)
21920 jasper_cdc
Medina-Interface-Reserved 4 jasper_coverage
Medina-Interface-Reserved 5 jasper_csr_opt
22650 jasper_dao
22800 jasper_fao
22810 jasper_fpv
24015 jasper_fpv_opt
24025 jasper_fst
24100 jasper_interactive (1)
24205 jasper_interactive_opt
BookmarkReader jasper_papp (1)
Collaboration_Ext_CatiaV5 (18) jasper_pcov
26000 jasper_pint (1)
DEPOCAM_INTF_PARASOLID jasper_sec
PROTOOLMAKER_5AXIS jasper_unr
Manikin_Analysis (26) jasper_vao
DEPOCAM_5AXIS Joules_Power_SP
ADVANCED_RENDER_2 (37) Joules_RTL_Power
29661 LAS_Cell_Optimization
RELEX_Telcordia (6) Layout (1)
Em.Sdk (2) LayoutEE (2)
Em.HyperCopy LayoutEngEd
30010 LayoutPlus
3002 LDPbaseCell
300_64bit LDPbaseGarray
3011 LDPclock
RELEX_217Plus (2) LDPhyperPlaceCell
RELEX_299B LDPhyperPlaceGarray
31000 LEAFPROG-SYS
RELEX_EventTree (2) LEAPFROG-BV
3111 LEAPFROG-C
RELEX_Maintainability (3) LEAPFROG-CV
RELEX_Markov LEAPFROG-SLAVE
RELEX_FaultTreeLite LEAPFROG-SV
Semantic_Anno LEAPFROG-SYS
32015 LEAPFROG-VC
32100 LEFDEF_IF
32101 libcompile
32110 Liberate_AMS_Client (1)
32120 Liberate_AMS_Server (1)
32125 Liberate_Client (2)
32130 Liberate_LV_Client
32140 Liberate_LV_Server
32150 (3) Liberate_LX_Client
32190 Liberate_LX_Server
PVECADPRO Liberate_MX_Client
32500 Liberate_MX_Server
32501 Liberate_Server (1)
32502 license
32503 LicFileVersion
32505 LID10
32510 LID11
32520 LINAR_LIB
32521 LINEAR-LIB
32530 LINEAR_LIB
32550 Litho_DP_Client
32600 Litho_Electrical_Analyzer
32610 Litho_Hotspot_Fixing
32620 Litho_Physical_Analyzer
32630 Low_Power_Simulation_Option
32640 LPE
32760 (6) LP_Methodolog_L
32_28nm_to_10nm LSE
33000 lwb
33010 MAG_LIB
33011 MaskCompose_Core
33015 MaskCompose_Definition
33016 MaskCompose_FracP_JobD
33100 MaskCompose_Implementation
33300 MaskCompose_OASIS
33301 MaskCompose_Paperwork
ObjectToolkitJavaRuntime (13) MaskCompose_SemiP10
33500 MaskCompose_Utils
33580 MaskCompose_Wafer
PTC_Creo_Unite mdin
3405 mdout
34500 (1) mdtoac
34510 mdtocv
34511 MIXAD_LIB
34530 MM_ddr3sdram
34570 MM_ddr4sdram
34580 MM_ddr4_lrdimm
35100 MM_emmc_45
35200 MM_emmc_50
SNEAKPEEK_MODE (8) MM_flash_onfi3
SHUTOFF_FACES (11) MM_flash_ppn_ddr
GRANITE_EXTENSION MM_flash_toggle2_nand
365_64bit MM_hbm
GDT_ENTERPRISE (7) MM_HMC
CFD_BASIC (10) MM_lpddr3
37100 MM_lpddr4
CFD_ADVANCE_PLUS MM_lrdimm
Materialise_Support (7) MM_PORTFOLIO_CATALOG
38500 MM_PORTFOLIO_PLUS_B
38520 MM_sdcard30
39000 MM_sdcard40
39001 MM_UFS
3DEM (2) MM_wideIOsdram
3DEMENG (2) MM_wideIO_2
3D_FieldSolver_Engine Model_Based_Verif_L
4000 Model_Check_Analysis
40020 Modus_common_ui (14)
40030 Modus_DFT_Opt (28)
40040 Modus_Diagnostics (7)
40500 Modus_Hierarchical_Opt
41000 Modus_LBIST_Opt
50000 Modus_PMBIST_Opt
50010 Modus_Test (19)
501 MP_HPC_Token
50110 MSMV
50200 MTI_option_Attsim
502A MTI_Opt_Incisive_Specman_Sim
5100 Multithread_Route_Option
51022 multiwire
51023 MV_4S40PUC_ALL
51060 MV_6SUPUC_ALL
51070 NanoRoute_Ultra
51170 Nano_Encounter
550 Nano_Encounter_DBS
COM/FOX-VDAFS_W NC-simulator
61300 NCSim_Desktop
61400 ncsysc_specman
681 NCVLOG_CGOPTS
7000 nc_specman
70000 NC_SystemC_Simulator
70110 NC_SystemVerilog_Simulator
70110_64bit NC_Verilog_Compiler
70120 NC_Verilog_Data_Prep_Compiler
70120_64bit NC_Verilog_Option
70130 NC_Verilog_Simulator
70510 NC_Vhdl_Compiler
70510_64_bit NC_Vhdl_Option
70520 NC_Vhdl_Simulator
70520_64bit NeoCell
71110 Nihongoconcept
71110_64bit OA
71120 OASIS_RFDE
71130 OASIS_Simulation_Interface (4)
71510 odan
71520 OpenModeler
72110 OpenModeler_SFI
72120 OpenModeler_SWIFT
72130 OpenSim
72131 OpenWaves
72132 OptimizePI
72133 Optimizer (14)
72134 options
72135 OPT_VIS300_NG
72140 OrbitIO_Sys_PlanC
72150 OrCAD
727 OrCAD_Capture_CIS_option (24)
728 orcad_component_portal (13)
729 orcad_dfm_checker
730 orcad_documentation (1)
730_64bit OrCAD_EDM_Key (4)
733 OrCAD_EDM_Vault (4)
73510 OrCAD_EE_Designer_Plus (3)
73520 orcad_ee_expert_suite
761 orcad_expert_suite
780 OrCAD_FPGA_System_Planner
780_64bit orcad_library_builder (2)
900 orcad_panel_editor
9000 orcad_partner_fae_suite
90001 OrCAD_PCB_Designer (25)
920 OrCAD_PCB_Designer_Basics (5)
940 (2) OrCAD_PCB_Designer_PSpice (2)
945 (6) OrCAD_PCB_Editor (23)
950 OrCAD_PCB_Editor_Basics (4)
95100 orcad_pcb_expert_Suite (1)
95115 orcad_pcb_productivity
95120 OrCAD_PCB_Router (7)
952 OrCAD_PSpice_Systems_Sim
95200 OrCAD_PSpice_Systems_Visual
95210 OrCAD_Signal_Explorer (2)
95220 orcad_sigrity_erc
95255 OrCAD_Unison_EE (18)
95300 OrCAD_Unison_PCB (1)
95310 OrCAD_Unison_Ultra (1)
95320 Pacific_Noise_Analyzer
95400 packager
960 Package_Extraction_SuiteC
960_64bit PartitionOptimizer
963 partner
964 PAS_Assura_Drc_Generator
965 PAS_Assura_Lvs_Generator
966 PAS_Diva_Drc_Generator
972 PAS_Diva_Lvs_Generator
974 PAS_Dracula_Drc_Generator
991 PAS_Dracula_Lvs_Generator
992 PAS_ErrorCell_Generator
993 PAS_Graphical_Tech_Editor
994 PAS_Pcell_Generator
995 PB_2S10PUC_ALL
a2dxf PB_2S15PUC_ALL
aae-signalscan PB_2S20PUC_ALL
aae-signalscan-transaction PB_2S40PUC_ALL
aae-transaction-explorer PB_2S60PUC_ALL
AbGen PB_2SUPUC_ALL
ABIT PB_4S10PUC_ALL
ABVIP_AHB PB_4S40PUC_ALL
ABVIP_AXI PB_4S60PUC_ALL
ABVIP_DFI PB_4SUPUC_ALL
ABVIP_OCP PB_6S60PUC_ALL
ACC_VIP_ACE PB_6SUPUC_ALL
ACC_VIP_AHB PB_USUPUC_ALL
ACC_VIP_APB pcb_cursor
ACC_VIP_AXI_3_4 PCB_designer
ACC_VIP_DBI PCB_design_expert (2)
ACC_VIP_ETHERNET_1G_10G PCB_design_studio (61)
ACC_VIP_ETHERNET_25G50G PCB_Design_Workbench_PDM_Opt
ACC_VIP_ETHERNET_40G_100G PCB_Design_Workbench_XL (3)
ACC_VIP_HDMI_14 pcb_editor
ACC_VIP_I2C pcb_engineer
ACC_VIP_I2S PCB_Extract
ACC_VIP_KPD PCB_Extract_20
ACC_VIP_MPC pcb_interactive
ACC_VIP_MPDI PCB_librarian_expert (7)
ACC_VIP_PCIE_3 PCB_Library_Manager (1)
ACC_VIP_SATA_6G PCB_Library_Server_XL (2)
ACC_VIP_SCD PCB_Library_Workbench_XL (1)
Actel_FPGA pcb_prep
actomd pcb_review
ADE_ElectronStorm_Option PCB_SI_MultiGigabit
ADE_GXL_TC_Cockpit PCB_studio_variants
ADE_GXL_TC_DCM pcomp
ADE_GXL_TC_MismatchAnalysis Pearl
ADE_GXL_TC_MTS Pearl_Cell
ADE_GXL_TC_Optimizer Pegasus_05nm
ADE_GXL_TC_PAD Pegasus_16nm
ADE_GXL_TC_SensitivityAnalysis Pegasus_advdrc
ADE_GXL_TC_Tuner Pegasus_advlvs
ADE_GXL_TC_YieldAnalysis Pegasus_core_10T_32
ADE_GXL_TC_YieldOptimizer Pegasus_DesignReview_Layout
ADE_VoltageStorm_Option Pegasus_DesignReview_Mask
AdvancedPI Pegasus_dfmfill
AdvancedSI Pegasus_DRC
Advanced_Cell_Placer Pegasus_int
advanced_FF_modeling Pegasus_LVS
advanced_modeling_20 Pegasus_mpt
Advanced_Package_Designer Pegasus_RV
Advanced_Pkg_Engineer_3D Pegasus_UI
Advanced_Pkg_Router_Option Performance_Option_To_Incisive (2)
Advanced_sub_10nm_modeling (1) PE_Librarian
Advanced_sub_5nm_modeling Physical_Verification_Sys
ADV_2S10PUC_ALL Physical_Verification_Sys_Deb
ADV_2S15PUC_ALL Physical_Verification_Sys_L
ADV_2S20PUC_ALL Physical_Verification_Sys_XL
ADV_2S40PUC_ALL Phys_Ver_Sys_ADP_Ex_Opt
ADV_2S60PUC_ALL Phys_Ver_Sys_Adv_Ana_Opt (5)
ADV_2SUPUC_ALL Phys_Ver_Sys_Adv_Device
ADV_4S10PUC_ALL Phys_Ver_Sys_Const_Validator
ADV_4S20PUC_ALL Phys_Ver_Sys_Cons_Validator_XL
ADV_4S40PUC_ALL Phys_Ver_Sys_DesignReview
ADV_4S60PUC_ALL Phys_Ver_Sys_Design_Ana (2)
ADV_4SUPUC_ALL Phys_Ver_Sys_DRC_XL (19)
ADV_6S60PUC_ALL Phys_Ver_Sys_Graph_LVS_Debug
ADV_6S90PUC_ALL Phys_Ver_Sys_Hier_DFM_SO_Opt
ADV_6SUPUC_ALL Phys_Ver_Sys_Int_Short_Loc_Opt
Adv_Encrypt_Std_64bit (1) Phys_Ver_Sys_LVS_XL (20)
Adv_IBIS_Modeling Phys_Ver_Sys_MRC
adv_package_designer Phys_Ver_Sys_Pattern_Match
adv_package_designer_expert Phys_Ver_Sys_Prog_ERC
adv_package_engineer_expert Phys_Ver_Sys_Prog_ERC_XL
ADV_VIS200_NG Phys_Ver_Sys_Quick_View
affirma-signalscan Phys_Ver_Sys_Results_Mgr (24)
affirma-signalscan-control Phys_Ver_Sys_Results_Viewer
affirma-signalscan-pro Phys_Ver_Sys_Yield_Enh_Opt
affirma-signalscan-schmatic PICDesigner
affirma-signalscan-source PIC_Utilities
affirma-signalscan-transaction pillar.abstract
affirma-transaction-explorer pillar.areaPdp
Affirma_3rdParty_Sim_Interface pillar.areaPlanner
Affirma_accel_transistor_sim pillar.cdsIn
Affirma_advanced_analysis_env pillar.cdsOut
Affirma_AMS_distrib_processing pillar.cellPdp
Affirma_ams_simulator pillar.cellPlanner
Affirma_equivalence_checker pillar.db
Affirma_equiv_checker_prep pillar.dbdev
Affirma_model_checker pillar.dbperl
Affirma_model_packager_export pillar.defIn
Affirma_NC_Simulator (4) pillar.defOut
Affirma_NC_VHDL_Desktop_Sim pillar.dpdev
Affirma_RF_IC_package pillar.dpuxIn
Affirma_RF_IC_package_modeler pillar.dpuxOut
Affirma_RF_SPW_model_link pillar.edifIn
Affirma_sim_analysis_env (85) pillar.edifOut
Affirma_transaction_analysis pillar.gatePdp
Affirma_trans_logic_abstracter pillar.gatePlanner
Allego_design_expert pillar.gdsIn
Allego_design_expert_620 pillar.gdsOut
allegroprance pillar.ge
AllegroSigrity_HS_Base_Suite pillar.gui
AllegroSigrity_PI_Base (5) pillar.ldexpand
AllegroSigrity_PI_Signoff_Opt (4) pillar.lefIn
AllegroSigrity_Pkg_Extract_Opt pillar.lefOut
AllegroSigrity_Pwr_Awr_SI_Opt (2) pillar.pdp
AllegroSigrity_Serial_Link_Opt (1) pillar.verIn
AllegroSigrity_SI_Base (5) pillar.verOut
AllegroSLPS pillar.vhdlIn
Allegro_Adv_Packaging_Plus pillar.vhdlOut
Allegro_Auth_HighSpeed_Option (3) pillar.vre
Allegro_Auth_MultiStyle_Opt pillar.xl
Allegro_CAD_Interface pillar.xlcm
Allegro_Designer (2) pillar.xldev
Allegro_Designer_Package_620 Pkg_Extract
Allegro_designer_suite PKIT1006
Allegro_Design_Editor_620 PKS
Allegro_Design_Entry PlaceBase
Allegro_design_expert (2) PlaceBase_ALL
Allegro_Design_Publisher (5) placement
allegro_dfa Placement_Based_Optimization
allegro_dfa_att Placement_Based_Synthesis
Allegro_ECAD_MCAD_Lib_Creator (2) PlaceOrIPlace_ALL
Allegro_Enterprise_PCB_Designe PLD
Allegro_Expert plotVersa
Allegro_FPGA_System_2FPGA PowerAnalysis
Allegro_FPGA_System_Planner_L (2) PowerDC (3)
Allegro_FPGA_System_Planner_XL PowerIntegrity
Allegro_FPGA_System_Plan_GXL PowerSI (1)
Allegro_ICPDesignPartition_Opt Power_Aware_SI_SuiteC
Allegro_Librarian Power_Integrity_SuiteC
allegro_non_partner PPC_Image_Decomposer
Allegro_Packager_Designer_620 PPR-HPPA
Allegro_Package_620 PPRoute
Allegro_Package_Designer_620 PPRoute_ALL
Allegro_Package_Designer_XL_II PP_2SUPUC_ALL
Allegro_Package_SI_620 PP_4S40PUC_ALL
Allegro_Package_SI_620_Suite PP_4S60PUC_ALL
Allegro_Package_SI_L_II PP_6S60PUC_ALL
Allegro_PCB PP_6S90PUC_ALL
Allegro_PCBSI_Backplane PP_6SUPUC_ALL
Allegro_PCBSI_Performance Prevail_Board_Designer
Allegro_PCBSI_SerialLink Prevail_Correct_By_Design
Allegro_PCBSI_SParams Prevail_Designer
Allegro_PCB_Design_230 Preview_Synopsys_Interface
Allegro_PCB_Design_620 Protel_IF
Allegro_PCB_Design_GXL PSpice (1)
Allegro_PCB_Design_Planner PSpiceAA (3)
Allegro_PCB_DFM_Checker PSpiceAAOptimizer
Allegro_PCB_Editor_GXL PSpiceAAStudio
Allegro_PCB_Global_Route_Env PSpiceAD (11)
Allegro_PCB_Harmony_Option PSpiceBasics
Allegro_PCB_HighSpeed_Option (19) PSpiceOptimizer
Allegro_PCB_Intercon_Feas (6) PSpiceOPTIOpt
Allegro_PCB_Intercon_Flow_Desn PSpicePerfOpt
Allegro_PCB_Interface PSpiceSLPSOpt
Allegro_PCB_Manufacturing PSpiceSmokeOpt
Allegro_PCB_Mini_Option (15) PSpiceStudio (2)
Allegro_PCB_Partitioning (2) PSpice_SLPS
Allegro_PCB_PDN_Analysis ptc_in
Allegro_PCB_Productivity_TB (4) ptc_out
Allegro_PCB_RF (2) PVS_MPT_Image_Decomposer
Allegro_PCB_Router_210 PVS_MPT_Spacer_Decomposer
Allegro_PCB_Router_230 PWM_LIB
Allegro_PCB_Router_610 QPlace
Allegro_PCB_SI_230 QRCX_Display_Technology_Option
Allegro_PCB_SI_620 QRC_Advanced_Analysis (2)
Allegro_PCB_SI_630 QRC_Advanced_Modeling (11)
Allegro_PCB_SI_630_Suite QRC_Advanced_Modeling_20 (4)
Allegro_performance (58) QRC_Advanced_Node_Modeling (7)
Allegro_performance_designer (1) QRC_NEXT_GENERATION
Allegro_Pkg_Designer_620 quanticout
Allegro_Pkg_Designer_620_Suite Quickturn_Model_Manager
Allegro_PSpice_Systems_Sim QuickView_CH_SL
Allegro_PSpice_Systems_Visual QuickView_GDSII
Allegro_Rel_Rules_Checker QuickView_GL1
Allegro_Rel_Rules_Developer QuickView_HITACHI
Allegro_RF_Modules_option_630 QuickView_JEOL
Allegro_SIP_Designer_630 QuickView_LAFF
Allegro_SLPS QuickView_MEBES
Allegro_studio (61) QuickView_OA
Allegro_studio_Router_610 QuickView_OASIS
Allegro_Symbol QuickView_SemiP10
Allegro_TeamDesign_Auth_Option QuickView_Signoff
Allegro_Venture_PCB_Designer (3) QuickView_TOSHIBA
Allegro_Venture_SDA RapidPART
Allegro_Viewer_Plus (25) rapidsim
ALL_EBD RB_2S10PUC_ALL
Altera_MAX RB_2S15PUC_ALL
Ambit_BuildGates RB_2S20PUC_ALL
Ambit_libcompile RB_2S40PUC_ALL
Ambit_RnD_option RB_2S60PUC_ALL
AMD_MACH RB_2SUPUC_ALL
AmoebaPlace RB_4S10PUC_ALL
AMS_CONNECTOR (1) RB_4S20PUC_ALL
AMS_Designer_Link RB_4S40PUC_ALL
AMS_Designer_Verification RB_4S60PUC_ALL
AMS_Designer_XL_Addon RB_4SUPUC_ALL
AMS_environment (2) RB_6S60PUC_ALL
AMS_Methodology_Kit RB_6S90PUC_ALL
AMS_Methodology_Kit_L RB_6SUPUC
AMS_Option_to_Incisive RB_6SUPUC_ALL
AMS_utilities RC-GXL
Analog_Design_Environment_GXL (5) RC-L
Analog_Design_Environment_L (20) RCExtraction
Analog_Design_Environment_XL (51) realchiplm
ANALOG_WORKBENCH redifnet
APD Relational_DRC_PCB_Developer
apd1 Relational_DRC_PCB_User
APR-HPPA Relational_DRC_SiP_Developer
Aptivia Relational_DRC_SiP_User
archiver RELXPERT (1)
arouter Rereading
Artist_Optimizer RF_SIP_Kit
Artist_Statistics Route
Assertion_Based_VIP_AXI4_ACE RouteADV
Assura_DRC (2) RouteADV_ALL
Assura_DV_design_rule_checker RouteBase
Assura_DV_LVS_checker RouteBase_ALL
Assura_DV_parasitic_extractor RouteDF
Assura_LVS (2) RouteDFM
Assura_MP (1) RouteDFM_ALL
Assura_OPC RouteFST
Assura_RCX RouteFST_ALL
Assura_RCX-FS RouteHYB
Assura_RCX-HF RouteHYB_ALL
Assura_RCX-MP RouteMin_ALL
Assura_RCX-PL RouteMVIA_ALL
Assura_RCX_Adv_Process RouteOrEdit_ALL
Assura_SI rt
Assura_SI-TL RTL_Compiler_Adv_Phys_Option
Assura_SiMC RTL_Compiler_CPU_Accel_Option
Assura_SiVL RTL_Compiler_L
Assura_UI (2) RTL_Compiler_Low_Power_Option
Atmel_ATV RTL_Compiler_L_Option
Attsim_option_ATS RTL_Compiler_Physical
auErc RTL_Compiler_RD
Aurora (2) RTL_Compiler_Ultra (5)
AWBAA RTL_Compiler_Ultra_II_Option
AWBAdvancedAnalysis RTL_Compiler_Verification
AWBSimulator Schematic_Generator
AWB_Batch SDL_IF
AWB_BEHAVIOR sdrc_in
AWB_DIST_SIM sdrc_out
AWB_MAGAZINE SDT_MODEL_MANAGER
AWB_MAGNETICS sepks
AWB_MIX Serial_Link_SI_SuiteC
AWB_PPLOT shapefill
AWB_RESOLVE_OPT SignalIntegrity
AWB_SIMULATOR SignalStorm_Lib_Characterizer
AWB_SMOKE Signalstorm_NDC
AWB_SPICEPLUS SignalStorm_Parallel_Sim
AWB_STATS signal_explorer
Base_Digital_Body_Lib Signal_Integrity
Base_Verilog_Lib SigNoise
BG (1) SigNoiseCS
BlockMaster_Characterizer SigNoiseEngineer
BlockMaster_Optimizer SigNoiseExpert
BlockPlace SigNoiseStdDigLib
BoardQuest_Designer SigNoise_Float
BoardQuest_Team SigTherm_CFD
BOGUS SigTherm_Signoff
BRDST_IF Sigxp
BroadbandSPICE sigxp_explorer
BuildGates Sigxp_tier
BuildGates_Extreme Sigxp_tier_EXPERT
Cadence_3D_Design_Viewer SiliconQuest
Cadence_chip_assembly_router SiliconQuest_CTGen_Option
Cadence_Chip_IO_Planner Silicon_Ensemble
Cadence_Chip_Optimizer Silicon_Ensemble_CTS
Cadence_CTS Silicon_Ensemble_DSM
Cadence_Framework_Runtime Silicon_Ensemble_DSM_Crosstalk
Cadence_Precision_Router Silicon_Ensemble_OpenDev
Cadence_Software_Developer Silicon_Ensemble_OpenExe
Cadence_Software_Developer_Dbg Silicon_Ensemble_WARP
Cadence_Software_Developer_OS Silicon_Synthesis_QPBS
Cadence_Spacebased_Router SimControl
Cadence_System_Creator SimVision
Cadence_System_Creator_801 Sim_Cov_UNR
Cadence_System_Creator_Inter SiP_Digital_Architect_GXL
Cadence_System_Creator_VSPCat SiP_Digital_Architect_GXL_II
Cadence_VSP_Eclipse_env_Debug SiP_Digital_Architect_L
Cadence_VSP_Eclipse_env_OS SiP_Digital_Architect_XL
Cadence_VSP_Fab SiP_Digital_Layout_GXL
CADIF_IF SIP_Digital_Layout_GXL_II
caeviews SiP_Digital_SI_XL
cals_out SiP_Digital_SI_XL_II
Capture (27) SiP_Layout_Option
CaptureCIS (13) SiP_Layout_XL (2)
Capture_CIS_Studio (36) SiP_RF_Architect
CATENA_QRC_FEATURE_REVISION SiP_RF_Architect_L
CATENA_SOC_FEATURE_REVISION SiP_RF_Architect_XL
catia (2) SiP_RF_Layout_GXL
cbds_in SiP_RF_Layout_GXL_II
CCAR SIP_RF_Layout_Option
CCD_Multi_Constraint_Check SIP_WLCSP
CCP SI_Timing_Convergence
CCPO SI_Timing_Convergence_VS
CDMA_Simulation_Runtime skillDev (1)
CDNS_ESW_DBG SLNK (1)
CDS_ENABLE_CHIP_OPTIMIZER SLOG:
cdxe_in SMG_Create
CELL3 SMG_Runtime
CELL3_ARO soce
CELL3_CROSSTALK SOC_2012_special
CELL3_CTS SOC_Encounter
CELL3_DIST SOC_Encounter_GPS
CELL3_ECL SOC_Encounter_GXL
CELL3_OPENDEV SOC_Encounter_L
CELL3_OPENEXE SOC_Encounter_XL
CELL3_PA SoC_Kit
CELL3_PR SOC_PORTFOLIO_CATALOG
CELL3_QPLACE SOC_PORTFOLIO_PLUS_B
CELL3_QPLACE_TIMING SoC_Verification_Kit
CELL3_QROUTE SONYBNTI
CELL3_RGT Space_based_Router
CELL3_SCAN SPB_500_NG
CELL3_TIMING SPDGEN (1)
CELL3_WIDEWIRE SPDSIM
Celsius_CFD_Opt SPECCTRAQuest (1)
Celsius_Thermal SPECCTRAQuest_EE
Celsius_ThermalG SPECCTRAQuest_EE_SI
celtic SPECCTRAQuest_Planner
Celtic_Crosstalk_Analyzer SPECCTRAQuest_signal_expert
Celtic_NDC SPECCTRAQuest_signal_explorer
CHDL_DesignAccess SPECCTRAQuest_SI_expert (1)
CheckADV_ALL SPECCTRA_256U
CheckPlus SPECCTRA_6U
Checkplus_Expert SPECCTRA_ADV
Chip_Integration_Option SPECCTRA_APD
Chip_Integration_Option_II SPECCTRA_autoroute (5)
CHN_VIS400_NG specctra_designer
CICNG_801 SPECCTRA_DFM
CICNG_802 SPECCTRA_expert
Cierto_HW_design_sys_2000 SPECCTRA_expert_system
Cierto_signal_proc_wrksys_2000 SPECCTRA_HP (8)
Cierto_SPW_CDMA_Library SPECCTRA_PCB (8)
Cierto_SPW_comm_library_fxp_pt SPECCTRA_performance (1)
Cierto_SPW_comm_lib_flt_pt SPECCTRA_QE
Cierto_SPW_GSM_VE SPECCTRA_Unison_PCB
Cierto_SPW_IS136_VE SPECCTRA_Unison_Ultra
Cierto_SPW_link_to_Ambit_BG SPECCTRA_VT
Cierto_SPW_link_to_NC_sim SpecialRoute
Cierto_SPW_model_manager specman
Cierto_SPW_multimedia_kit Specman_Advanced_Option
Cierto_SPW_pcscdma_VE SpectreBasic
Cierto_Wireless_LAN_Library SpectreHDL
CISOption SpectreRF
Clarity_3DSolver Spectre_AMSD_Lk
Clarity_3DSolverG Spectre_AMS_MMSIM_Lk (21)
ClockSyn Spectre_APS_Verification (4)
Clock_Tree_Generation Spectre_BTAHVMOS_Models
CMP_Copper_Prediction_CDN Spectre_BTASOI_Models
CMP_PO_Predic_Cali_Cu Spectre_Burst_AllegroSI
CMP_PO_Predic_Cali_Cu_Etch_PMD Spectre_char_opt (1)
CMP_Predictor Spectre_EMIR
CMP_Predictor_BEOL_MOL Spectre_Fault_Analysis_opt
CMP_Predictor_Cu spectre_FX_sc
CMP_Predictor_Cu_Etch_PMD Spectre_Interactive_mode
CMP_Process_Optimizer Spectre_NorTel_Models
CMP_TSMC_VCMP_CDN Spectre_Parallel_Analysis
CMP_Viewer Spectre_Siemens_Models
Cobra_Simulator Spectre_ST_Models
comp Spectre_XPS
compose Spectre_X_MMSIM_Lk (7)
ComposerCheckPlus_AdvRules SPICE_IF
ComposerCheckPlus_Checker SPW (2)
ComposerCheckPlus_RuleDev SPW_BDE
Composer_EDIF300_Connectivity SPW_BER_Sim
Composer_EDIF300_Schematic SPW_BVHDL_CDMA_LIB
Composer_Schematic_Generator SPW_BVHDL_COMM_FXP
Composer_Spectre_Sim_Solution SPW_CGS_
compose_autoplan SPW_CGS_ANY
compose_gcr SPW_CGS_C30
compose_scells SPW_CGS_C40
compose_tlmr SPW_CGS_DSP32C
compose_util SPW_CGS_M96002
concept SPW_CGS_PKB
Concept-HDL SPW_CGS_STANDARD_C
ConceptHDL SPW_COSIM_LEAPFROG
conceptXPC SPW_COSIM_VERILOG_XL
Concept_HDL_expert SPW_COSIM_VSS
Concept_HDL_rules_checker SPW_DATA_MANAGEMENT
Concept_HDL_studio (12) SPW_ENV_MAT
ConcICe_Option SPW_FDS
Conformal_Asic (8) SPW_FMG
Conformal_Cnstrnt_Dsgnr_L_LL SPW_FSM
Conformal_Cnstrnt_Dsgnr_XL_LXL (2) SPW_HDS_VHDL_LINK
Conformal_Constraint_Designer SPW_HLS
Conformal_Constraint_Dsgnr_XL SPW_LIB_CDMA_LIB
Conformal_Custom SPW_LIB_COMM_FXP
conformal_datapath SPW_LIB_COMM_LIB
Conformal_ECO (1) SPW_LIB_DSP1600
Conformal_ECO_GXL SPW_LIB_DSP563S
Conformal_GXL SPW_LIB_DSP566S
conformal_ldd (3) SPW_LIB_DSP568S
conformal_lec (3) SPW_LIB_DSPGROUP
Conformal_Low_Power (28) SPW_LIB_GSM_LIB
Conformal_Low_Power_GXL SPW_LIB_HDS_ARC
Conformal_LP_GXL SPW_LIB_HDS_ISL
conformal_lvr SPW_LIB_HDS_LIB
conformal_mem SPW_LIB_HDS_MAIN
Conformal_Smart_LEC_4CPU SPW_LIB_HDS_MICRO
Conformal_Ultra (2) SPW_LIB_IS136LIB
conformal_vhd (3) SPW_LIB_IS95LIB
conformal_vlg (3) SPW_LIB_ISL
Corners_Analysis SPW_LIB_M5630X
COSLITE_ACCESS (12) SPW_LIB_MATLAB
coverscan-analysis SPW_LIB_MDK
coverscan-recorder SPW_LIB_RADAR
cpe SPW_LIB_RF_LIB
CPF (4) SPW_LIB_SGSTHOMSON
cpte SPW_LIB_TIC54X
CPtoolkit SPW_LIB_TIC5X
CP_Ele_Checks SPW_LIB_VFL
crefer SPW_LINK_VERILOG
CTE SPW_LINK_VHDL
cvtomd SPW_LINK_VHDL_BEH
CWAVES SPW_LSF_Link
CWB01 SPW_MODEL_MANAGER
CWB03 SPW_MPX
CWB04 SPW_SIGCALC
CWB05 SPW_SIM
C_to_Silicon_Compiler_L SPW_SIM_UI
C_to_Silicon_Compiler_RC SPW_Smart_Antenna_Library
Datapath_Preview_Option sqpkg
Datapath_Verilog SQ_Digital_Logic_SI_Lib
Datapath_VHDL SQ_FPGA_SI_Lib
debug SQ_Memory_SI_Lib
Debug_Option_to_Incisive SQ_Microprocessor_SI_Lib
DelayCal SQ_ModelIntegrity
Designer_System_Capture Stratus_FloatingPoint
DesignViewer Stratus_HLS_L
desktop_manager Stratus_HLS_XL
Desktop_mgr Stratus_IDE
Device_Level_Placer stream_in
Device_Level_Router stream_out
DFM_2S10PUC_ALL StudioPSpiceAD
DFM_2S15PUC_ALL STV90a
DFM_2S20PUC_ALL Substrate_Coupling_Analysis
DFM_2S40PUC_ALL Substrate_Noise_Analyst
DFM_2S60PUC_ALL sv_surecov
DFM_2SUPUC_ALL sv_suresight
DFM_4S10PUC_ALL swap
DFM_4S20PUC_ALL SWIFT
DFM_4S40PUC_ALL sx
DFM_4S60PUC_ALL Synlink_Interface
DFM_4SUPUC_ALL synSmartIF
DFM_6S60PUC_ALL synSmartLib
DFM_6S90PUC_ALL synTiOpt
DFM_6SUPUC_ALL SystemSI_Parallel_IIC (1)
DFM_Core_Technology (5) SystemSI_Serial_IIC
dfsverifault SystemSI_Suite
DICRETE_LIB System_Verifier_generation
Digital_Mixed_Signal_Option System_Verifier_interactive
DISCRETE_LIB T2B
Distributed_Dracula_Option TANCELL
DPbase team_design_orcad
DPbaseCell Tempus_Timing_Signoff_L (36)
DPbaseGarray Tempus_Timing_Signoff_MP
DPcctIcCraft Tempus_Timing_Signoff_PI_opt
DPcdsBE Tempus_Timing_Signoff_TSO (1)
DPcdsC3 Tempus_Timing_Signoff_XL (7)
DPcdsCE Tempus_Timing_Signoff_XX
DPcdsGE Test_Design_Analysis (1)
DPcdsPar Test_Design_ATPG_Plus
DPcongest Test_Design_Compression
DPdelayCalc Test_Design_Generation (1)
DPecoIpo Test_Design_Verification
DPextractRC Test_Extension_Language (1)
DPfasnet Test_Mfg_Analysis
DPgotc Test_Mfg_Fault_Isolation
DPhyperPlaceCell Thick_Model_MultiCPU
DPhyperPlaceGarray TimingAnalysis
DPparasitic TimingBudget
DPpearlLocked TOPOLOGY_EDITOR
DPqplaceAB transformal_ltx
DPqplaceGA Trans_level_option_Attsim
DPqplaceLocked TrialRoute
DPrcExtract tscr
DPsdfConvPR tscr.ex
DPsynopsys tsTestGen
DPunivInterface tsTestIntf
DPwplaceLocked tsTSynVHDL
DRAC2CORE tsTSynVLOG
DRAC2DRC tune
DRAC2LVS tw01
DRAC3CORE tw02
DRAC3DRC UET
DRAC3LVS ULMdelta
DRACACCESS ULMecho
DRACDIST ULMhotel
DRACERC ULMindia
DRACLAYDE ULMjuliette
DRACLPE ULMmike
DRACLVS ULTRASIM
DRACPG_E ULTRASIM_GXL
DRACPLOT ULTRASIM_L
DRACPRE Unison_SPECCTRA_4U
DRACSLAVE UNISON_SPECCTRA_6U
dracula_in Universal_Smartpath
dxf2a Updating
e2v Use_Server_Options
EAD100_NG v2e
EAD_EM_Analysis Vampire_HDRC
EAD_FEATURE_REVISION Vampire_HLVS
EAD_MBL_Extraction Vampire_MP
EBD_edit Vampire_RCX
EBD_floorplan Vampire_UI
EBD_power Variery_MX_Server
EB_2S10PUC_ALL Variety_Client
EB_2S15PUC_ALL Variety_LX_Client (1)
EB_2S20PUC_ALL Variety_LX_Server (1)
EB_2S40PUC_ALL Variety_MX_Client
EB_2S60PUC_ALL Variety_MX_Server
EB_2SUPUC_ALL Variety_Server
EB_4S10PUC_ALL VB_2S10PUC_ALL
EB_4S20PUC_ALL VB_2S15PUC_ALL
EB_4S40PUC_ALL VB_2S20PUC_ALL
EB_4S60PUC_ALL VB_2S40PUC_ALL
EB_4SUPUC_ALL VB_2S60PUC_ALL
EB_6S60PUC_ALL VB_2SUPUC_ALL
EB_6S90PUC_ALL VB_4S10PUC_ALL
EB_6SUPUC_ALL VB_4S20PUC_ALL
eCapture VB_4S40PUC_ALL
ECO VB_4S60PUC_ALL
edif-HPPA VB_4SUPUC_ALL
edif2ged VB_6S60PUC_ALL
EDIF_Netlist_Interface VB_6S90PUC_ALL
EDIF_Schematic_Interface VB_6SUPUC
EditBase VB_6SUPUC_ALL
EditBase_ALL VB_USUPUC_ALL
EditFST vc-signalscan
EditFST_ALL vc-signalscan-transaction
EditPlace_ALL vc-transaction-explorer
EditRoute_ALL VCC_Editors
EDI_CPU_Accelerator_GXL VCC_links_to_implementation
EDI_System_Block_Design VCC_Simulators
EDI_System_Hier_Design VCC_SW_Estimator
EDS-BLK VCR
EDS_BLK VCS_Opt_Incisive_Specman_Sim
EF_2SUPUC_ALL Vdixl_Capacity_Opt
EF_4S40PUC_ALL VDI_XL_Capacity_Opt
EF_4S60PUC_ALL VDS_Power
EF_4SUPUC_ALL VDS_Timing
EF_6S60PUC_ALL verfault
EF_6S90PUC_ALL verifault
EF_6SUPUC_ALL Verify
ElectronStorm_Transistor Verif_Ckpit_Analysis_Env
EMCdisplay Verif_Ckpit_Runtime_Env
EMControl VERILOG-SLAVE
EMControl_Float VERILOG-XL (13)
EMI_ALL Verilog_desktop
EMX_ModelGen Verilog_XL_Desktop
EMX_Solver (1) Verilog_XL_Turbo_NT
ENC-MCPU VERITIME
Encounter VERLOG-SLAVE
Encounter_Adv_Node_GXL (6) VFICNG_200
Encounter_Block vgen
Encounter_C (4) VHDLLink
Encounter_ccopt_GXL (1) VHDL_desktop
Encounter_Clck_Cncrnt_Opt_GXL viable
Encounter_ClockSyn ViewBase
Encounter_CPU_accelerator_GXL (1) ViewBaseEngr_ALL
Encounter_Design_Planner_XL ViewBase_ALL
Encounter_DFM VIP_802_11_MAC
Encounter_DFM_GXL VIP_AHB_UVC
Encounter_Diagnostics_Volume VIP_AMBA5_CHI
Encounter_Digital_Impl_Sys_L VIP_AXB_PS
Encounter_Digital_Impl_Sys_XL (7) VIP_AXI4_ACE
Encounter_GigaScale_GXL VIP_AXI4_STREAM
Encounter_Giga_Scale_GXL VIP_AXI_3_4
Encounter_Library_Char_GXL VIP_AXI_3_4_UVC
Encounter_Library_Char_XL VIP_AXI_PS
Encounter_Low_Power_GXL VIP_CAN
Encounter_Mixed_Signal_GXL VIP_CSI2_2
Encounter_NG100 VIP_DISPLAYPORT
Encounter_Power_System_L VIP_ETHERNET_25G (2)
Encounter_Power_System_XL VIP_ETHERNET_40G_100G_PS
Encounter_Pow_Sys_Adv_Anls_GXL VIP_ETHERNET_40G_100G_UVC
Encounter_QRC_Extraction_GXL VIP_ETHERNET_PS
Encounter_QRC_Extraction_L VIP_ETHERNET_TRIPLECHECK
Encounter_QRC_Extraction_XL VIP_ETHERNET_UVC (2)
Encounter_S20_GXL VIP_HDMI_14
Encounter_Stacked_Die_GXL VIP_HDMI_20
Encounter_Stack_Die_GXL VIP_I2C
Encounter_Stack_Die_Option VIP_INTERCONNECT_WORKBENCH
Encounter_T20_GXL VIP_JTAG
Encounter_Test_Architect VIP_LIN
Encounter_Test_CPF VIP_MHL3
Encounter_Test_ExtensionLang VIP_MIPI_CPHY
Encounter_Timing_System_GXL VIP_MIPI_CSI
Encounter_Timing_System_L VIP_MIPI_CSI_3
Encounter_Timing_System_XL VIP_MIPI_DSI
Encounter_Tim_Sys_Adv_Anls_GXL VIP_MIPI_LLI
Encounter_True_Time VIP_MIPI_MPHY
Encounter_U20_GXL (1) VIP_MIPI_SLIMBUS
Encounter_Wave_Viewer VIP_MIPI_SOUNDWIRE
Encounter_X VIP_MIPI_UNIPRO
ENC_MCPU VIP_MR_IOV_PS
Enc_Test_Adv_MBIST_option VIP_NVME_PS
Enc_Test_LBIST_option VIP_OCP
Enc_Test_Stack_Die_Option VIP_OCP3
enterprise_manager VIP_OCP_3
Envisia_DataPath_option VIP_PCIE_1_2_PS (1)
Envisia_DP_SI_design_planner VIP_PCIE_3_MPHY
Envisia_GE_ultra_place_route VIP_PCIE_3_PS
Envisia_LowPower_option VIP_PCIE_3_PURESUITE
Envisia_PKS VIP_PCIE_3_TRIPLECHECK
Envisia_RAC VIP_PCIE_4
Envisia_SE_SI_place_route VIP_PCIE_PURESUITE
Envisia_SE_ultra_place_route VIP_PCI_UVC
Envisia_synthesis_with_PKS VIP_PLB
Envisia_Utility VIP_PLB_6
ET_Hierarchical_Option vip_portfolio
evc_verisity_ahb VIP_PORTFOLIO_CATALOG (2)
evc_verisity_axi VIP_PORTFOLIO_PLUS_B
evc_verisity_enet VIP_PUREVIEW
evc_verisity_pci VIP_SAS
evc_verisity_pcie VIP_SAS_12G
evc_verisity_pcie_ep VIP_SATA_6G
evc_verisity_pcie_rc VIP_SATA_PS
evc_verisity_usb VIP_SRIO
evc_verisity_usb_otg VIP_SRIO3
expert VIP_SR_IOV_PS
expgen VIP_SSIC
EXPIRED: VIP_UART
explorer (3) VIP_UNIPRO_TRIPLECHECK
Express VIP_USB31
ExpressPlus VIP_USB_2_PS
Extended_Digital_Body_Lib VIP_USB_3_PS
Extended_Digital_Lib VIP_USB_3_PURESUITE
Extended_Verilog_Lib VIP_UVC_3PSI_ENGINE
fcengine VIP_VALIDATOR_BASIC
fcheck VIP_VALIDATOR_COHERENT
feature virtuosoCCO
feature001 (2) virtuosoRDE
fethman Virtuoso_Acceler_Parallel_L
fetsetup Virtuoso_Acceler_Parallel_sc (2)
FE_ASIC Virtuoso_Acceler_Parallel_XL
FE_ASIC_Agere Virtuoso_ADE_Assembler (16)
FE_ASIC_Fujitsu Virtuoso_ADE_Explorer (18)
FE_ASIC_IBM Virtuoso_ADE_Explorer_Basic
FE_ASIC_LSILogic Virtuoso_ADE_Verifier
FE_ASIC_Mitsubishi Virtuoso_Adv_Dev_Modeling_ELDO
FE_ASIC_NEC Virtuoso_Adv_Dev_Mod_HSPICE
FE_ASIC_Philips Virtuoso_Adv_Node_Framework (4)
FE_ASIC_Samsung Virtuoso_Adv_Node_Opt_Layout (1)
FE_ASIC_ST Virtuoso_Adv_Node_Opt_Lay_Std (3)
FE_ASIC_TI Virtuoso_APS_MMSIM_Lk (7)
FE_ASIC_Toshiba Virtuoso_CFDE_Opt
FE_Classic virtuoso_chip_editor
FE_GPS VIRTUOSO_CM_OPTION_FOR_VSDE
FE_Ultra Virtuoso_Constraint_API
file... Virtuoso_Constraint_Interface
finaleco Virtuoso_Core_Characterizer
finaleIX Virtuoso_Core_Optimizer
finalePR Virtuoso_custom_placer
Finale_CO_Components Virtuoso_custom_router
Finale_IX Virtuoso_DFM_option
Finale_Router Virtuoso_Digital_Impl
Finale_XTS Virtuoso_Digital_Implem (9)
Fire_IceQXC2_Cell Virtuoso_Digital_implement
Fire_Ice_Cell Virtuoso_Digital_Implem_XL
Fire_Ice_Cell_NanoMeter Virtuoso_Digital_Impl_XL
Fire_Ice_Cell_Transistor Virtuoso_Digital_Signoff_Power
Fire_Parallel Virtuoso_DRC_Opt (1)
FirstEncounter Virtuoso_EAD_3D_Prec_Solver
FirstEncounterSOC Virtuoso_EAD_Adv_Elect_Analysi
First_Encounter Virtuoso_IPVS_Adv_Ana_Opt (1)
First_Encounter_GPS Virtuoso_Layout_Migrate
First_Encounter_GXL Virtuoso_Layout_Suite_EAD
First_Encounter_L Virtuoso_Layout_Suite_EXL (1)
First_Encounter_SOC Virtuoso_Layout_Suite_GX
First_Encounter_Ultra Virtuoso_Layout_Suite_GXL (19)
First_Encounter_VIP Virtuoso_Layout_Suite_L (22)
First_Encounter_XL Virtuoso_Layout_Suite_XL (66)
FloatPC_ALL Virtuoso_LDE_Analyzer
FloorPlan Virtuoso_MixedSignalOpt_Layout
fluke Virtuoso_MMSIM_CPU_Accelerator (2)
FNPLS-INTERNAL-CKPT1 Virtuoso_MMSIM_Incubation
Formal_Analysis_Option Virtuoso_MMSIM_pwr_opt
FPGA_Flows Virtuoso_MMSIM_RF_analysis
FPGA_OPTIMIZER Virtuoso_MultiTech_Framework (1)
FPGA_Tools Virtuoso_Multi_mode_Simulation (82)
Framework (2) Virtuoso_NeoCircuit_DFM
fsim Virtuoso_Oasis_API
FST_2SUPUC_ALL VIRTUOSO_OPT_OPTION_FOR_VSDE
FST_4S40PUC_ALL Virtuoso_Phase_Designer
FST_4S60PUC_ALL Virtuoso_Photonics_Option
FST_4SUPUC_ALL Virtuoso_Power_System_GXL
FST_6S60PUC_ALL Virtuoso_Power_System_L
FST_6S90PUC_ALL Virtuoso_Power_System_L_EXT
FST_6SUPUC_ALL Virtuoso_Power_System_XL (1)
Functional_Safety_Simulator Virtuoso_QRC_Extraction_GXL
FUNCTION_LIB Virtuoso_QRC_Extraction_L (3)
GATEENSEMBLE Virtuoso_QRC_Extraction_XL (33)
GATEENSEMBLE_ARO Virtuoso_RF_Platform
GATEENSEMBLE_CROSSTALK Virtuoso_Schematic_Editor_GXL
GATEENSEMBLE_CTS Virtuoso_Schematic_Editor_L (69)
GATEENSEMBLE_CTS_LE Virtuoso_Schematic_Editor_XL (60)
GATEENSEMBLE_CTS_UL Virtuoso_Schem_Option
GATEENSEMBLE_DIST Virtuoso_SiI
GATEENSEMBLE_ECL Virtuoso_Simulation_Interface
GATEENSEMBLE_LOWEND Virtuoso_Spectre (4)
GATEENSEMBLE_OPENDEV Virtuoso_Spectre_GXL
GATEENSEMBLE_OPENEXE Virtuoso_Spectre_GXL_MMSIM_Lk (27)
GATEENSEMBLE_PA Virtuoso_Spectre_RF
GATEENSEMBLE_PR_LE Virtuoso_Spectre_XL
GATEENSEMBLE_PR_UL VIRTUOSO_SPEC_DRIVEN_ENVIRO
GATEENSEMBLE_QPLACE Virtuoso_Sprectre_GXL_MMSIM_LK
GATEENSEMBLE_QPLACE_TIMING Virtuoso_Stack_Die_Option
GATEENSEMBLE_QROUTE Virtuoso_Turbo
GATEENSEMBLE_RGT Virtuoso_Turbo_Basic
GATEENSEMBLE_SCAN virtuoso_vale_framework
GATEENSEMBLE_TIMING Virtuoso_Variation_Analysis_Op
GATEENSEMBLE_TIMING_LE Virtuoso_Variation_Option
GATEENSEMBLE_TIMING_UL Virtuoso_Visual_Analysis_XL (4)
GATEENSEMBLE_UNLIMITED Virtuoso_Waveform_API
GATEENSEMBLE_WIDEWIRE Virtuoso_XL
Gate_Ensemble_DSM Virtuoso_XL_Basic
Gate_Ensemble_DSM_Crosstalk Virtuoso_XPS_MMSIM_Lk (8)
Gate_Ensemble_WARP visula_in
gbom VITAL-XL
GdsiiOut vloglink
GDS_IF VLS-GXL
GDT_IF VLS_GXL_TC_Analog_Auto_Placer
ged2edif VLS_GXL_TC_Cell_Planner
Genus_CPU_Opt (1) VLS_GXL_TC_Cockpit
Genus_Low_Power_Opt VLS_GXL_TC_Digital_Auto_Placer
Genus_Physical_Opt (1) VLS_GXL_TC_Floorplanning
Genus_Synthesis (37) VLS_GXL_TC_ISL
gilbert VLS_GXL_TC_Layout_CE
glib VLS_GXL_TC_Layout_Migrate
gloss VLS_GXL_TC_Layout_Yield_Optimi
gphysdly VLS_GXL_TC_Module_Generator
gscald VLS_GXL_TC_Space_based_Router
GSM_Simulation_Runtime VLS_GXL_TC_SPD
gspares VLS_GXL_TC_VCAR
HDL-DESKTOP VLS_GXL_TC_VLS_GXL
HLDexportDPUX VLS_GXL_TC_VPLGen
HLDimportDPUX vmanager
HLDSbase vmanager_client (4)
HLDSbaseC Vmanager_High_Availability
hp3070 vmanager_integration
HYB_2S10PUC_ALL vmanager_project (2)
HYB_2S15PUC_ALL vmanager_safety_client (1)
HYB_2S20PUC_ALL vmanager_ucis
HYB_2S40PUC_ALL vmanager_web
HYB_2S60PUC_ALL vm_app_multiproject
HYB_4S40PUC_ALL vm_app_multisite
HYB_4S60PUC_ALL VM_integ_opt
HYB_4SUPUC_ALL VoltageStorm_Cell_Transistor2
HYB_6S60PUC_ALL VoltageStorm_Transistor
HYB_6S90PUC_ALL VoltageStorm_Transistor_XL
HYB_6SUPUC_ALL VoltageStorm_UI
hyperExtract Voltus_Power_Integrity_AA (1)
hyperRules Voltus_Power_Integrity_AA_GXL
Ice_Parallel Voltus_Power_Integrity_ESD
ICP_Extract_20 Voltus_Power_Integrity_Fi_AA
IC_autoroute Voltus_Power_Integrity_Fi_L
IC_autoroute_ALL Voltus_Power_Integrity_Fi_XL
IC_devicegen Voltus_Power_Integrity_L
IC_devicegen_ALL Voltus_Power_Integrity_MP (1)
IC_deviceplace_ALL Voltus_Power_Integrity_XL (4)
IC_edit Voltus_Sigrity_PI
IC_editfast_ALL Voltus_Sigrity_PKG
IC_edit_ALL Voltus_Sigrity_SI_PI
IC_gcell_route VXL-ALPHA
IC_gcell_route_ALL VXL-LMC-HW-IF
IC_hsrules VXL-SWITCH-RC
IC_hsrules_ALL VXL-TURBO
IC_Inspector VXL-VCW
IC_InspectorEngr_ALL VXL-VET
IC_Inspector_ALL VXL-VLS
IC_mp_route VXL-VRA
IC_mp_route_ALL wedifsch
IC_power_route WinPlace
IC_power_route_ALL WireEdit
IDF_Bi_Directional_Interface WLAN_Simulation_Runtime
IE100_NG X4ENC
iges_electrical XBLOX-HPPA
Incisive_Advanced_Lint XceliumLimitedSingleCoreLegacy
Incisive_Design_Team_Simulator Xcelium_AMS_Option
Incisive_Desktop_Manager Xcelium_For_Partners
Incisive_Digital_Mixed_Signal Xcelium_Incubation_General (1)
Incisive_Enterprise_ESL_inter Xcelium_Limited_Single_Core (3)
Incisive_Enterprise_ESL_Option Xcelium_MC_GLS_SDF_Option
Incisive_Enterprise_Manager Xcelium_Multi_Core
Incisive_Enterprise_Planner Xcelium_Safety (1)
Incisive_Enterprise_Simulator (18) Xcelium_Safety_Option
Incisive_Enterprise_Verifier Xcelium_Safety_Sim
Incisive_Formal_Verifier Xcelium_SC_DMS_Option (22)
Incisive_HDL_Simulator (6) Xcelium_Single_Core (57)
Incisive_P2C_Methodology Xcelium_Single_Core_Legacy
Incisive_Safety_Simulator XcitePI_ExtractionC
Incisive_Specman_Elite XcitePI_Suite
Incisive_Specman_ESL XDE-HPPA
Incisive_Specman_ESL_inter xilCds
Incisive_Specman_interactive (1) xilComposerFE
Incisive_Verif_Engine (1) xilConceptFE
Incisive_Verif_Environ (1) xilEdif
Incisive_Virtual_Ext_inter Xilinx_FPGA
Incisive_Virtual_Ext_Option XtractIM (1)
Incisive_XLD_Domain _21900
Indago_DA_App